1. Field of the Invention
The present invention relates to a charge pump circuit which is a DC-DC converter of a charge pump type formed in a semiconductor integrated circuit.
2. Prior Art
In recent years, with the spread of portable electronic apparatuses required to save power, semiconductor integrated circuits used therefor have been required to be driven at a low power supply voltage. However, in semiconductor integrated circuits, there are cases where a voltage different from the power supply voltage is required for purposes such as the enhancement of the dynamic range. In such cases, a charge pump circuit is used as the circuit performing DC-DC voltage conversion.
In conventional charge pump circuits, the charge charged to the output capacitor at the time of activation is zero. For this reason, the output capacitor is rapidly charged, so that a large current flows momentarily and the output voltage changes abruptly.
In particular, when the output of a charge pump circuit is used as the negative power source in a semiconductor integrated circuit, since it is necessary that the substrate potential of the semiconductor integrated circuit be the lowest potential, the substrate is connected to the output of the charge pump circuit. Consequently, when the output of the charge pump circuit abruptly changes, the voltage change is transmitted to every part of the semiconductor integrated circuit through parasitic capacitance and this adversely affects the circuit operation.
Means for solving this problem is proposed in Japanese Laid-Open Patent Application No. 2003-18822. With reference to the circuit diagram of FIG. 6 showing the schematic structure of a charge pump circuit and the timing chart shown in FIG. 7, the operation of the charge pump circuit will be described. In FIG. 6, reference numerals 1 to 4 represent MOS transistors, reference numeral 5 represents a flying capacitor, reference numeral 6 represents an output capacitor, reference numeral 7 represents an oscillation circuit having the function of monitoring the output level and changing the duty ratio of the oscillation, reference numeral 9 represents the output terminal of the charge pump circuit, reference numeral 10 represents a dead time generation circuit, and reference numeral 11 represents a logic element formed of a NOT gate. FIG. 7 shows the changes, with time, of the gate input levels of the MOS transistors 1 to 4 from the time the charge pump circuit is activated to the time the output voltage is stabilized to effect a shift to the normal operation.
When the charge pump circuit is activated, a rectangular wave is outputted from the oscillation circuit 7, and the signals shown in FIG. 7 are inputted as the inputs to the gate terminals of the MOS transistors 1 to 4, respectively. By such signals being inputted, a cycle where the MOS transistors 1 and 2 are simultaneously turned on to charge the flying capacitor 5 and a cycle where the MOS transistors 3 and 4 are simultaneously turned on to discharge the flying capacitor 5 and charge the output capacitor 6 are alternately repeated. Then, the output level of the output terminal 9 is −VDD in the end.
At this time, in order that the MOS transistors 1 and 2 and the MOS transistors 3 and 4 are not simultaneously turned on, a dead time is added as the input signals to the gate terminals of the MOS transistors 3 and 4 by use of the dead time generation circuit 10.
In this series of steps, when the charge pump circuit is activated, the charge charged to the output capacitor 6 is zero as mentioned above. Therefore, if the flying capacitor 5 is completely charged in the cycle to charge the flying capacitor 5 at the first time, in the next cycle to discharge the flying capacitor 5, a large current flows through the output capacitor 6 to rapidly charge the output capacitor 6. Consequently, the output voltage level abruptly changes. To prevent this, at the oscillation circuit 7, the output voltage level is monitored and when the output voltage level is not less than a predetermined voltage, the duty ratio of the outputted rectangular wave is made low.
By performing control like this, the period during which the flying capacitor 5 is charged is reduced and this reduces the amount of charge charged to the flying capacitor 5 in one cycle, so that the amount of current flowing through the output capacitor 6 in the next discharging cycle is also reduced. Consequently, the drop in output voltage level is gentle. When the output voltage level becomes not more than a predetermined level, the oscillation circuit 7 increases the duty ratio of the rectangular wave to thereby ensure the charge supply capability for the output.
However, in the charge pump circuit proposed in Japanese Laid-Open Patent Application No. 2003-18822, no consideration is given to activating/deactivating the charge pump circuit other than when the power is turned on. In uses required to save power such as portable apparatuses, it is important to prevent loss of power by deactivating the charge pump circuit when it is not used.
To deactivate the charge pump circuit, in the charge pump circuit shown in FIG. 6, the MOS transistors 1 to 4 are all turned off by inputting a high level signal to the gate terminal of the MOS transistor 1 and inputting a low level signal to the gate terminals of the MOS transistors 2 to 4. However, in a case where the function of merely activating/deactivating the charge pump circuit as mentioned above is added to the charge pump circuit of FIG. 6, although the change in output voltage level is gentle when the charge pump circuit is activated for the first time, the output voltage level abruptly changes when the charge pump circuit is deactivated once and activated again.
This problem will be described with reference to FIG. 8. FIG. 8 is a circuit diagram in which the charge pump circuit activating/deactivating function is added to the above-described charge pump circuit shown in FIG. 6. FIG. 9 shows the changes, with time, of the gate input levels of the MOS transistors 1 to 4, and FIG. 10 is a view showing the changes, with time, of the average charge amount of the flying capacitor 5 and the output voltage. Elements corresponding to the elements described with reference to FIG. 6 and having equal functions are denoted by the same reference numerals, and overlapping descriptions thereof are omitted.
In FIG. 8, reference numeral 8 represents a charge pump activation/deactivation control circuit. When the charge pump activation/deactivation control circuit 8 outputs a high level signal, the charge pump circuit is activated, and when it outputs a low level signal, the charge pump circuit is deactivated. Reference numerals 12 and 15 represent logic elements formed of AND gates, and reference numerals 13 and 14 represent logic elements formed of NOT gates.
The operation from the time the charge pump circuit is activated for the first time to the time the output voltage is stabilized to effect a shift to the normal operation is similar to the above-described contents, and a high level signal is outputted from the charge pump activation/deactivation control circuit 8. When a low level signal is inputted from the charge pump activation/deactivation control circuit 8, a high level signal is inputted to the gate terminal of the MOS transistor 1 and a low level signal is inputted to the gate terminals of the MOS transistors 1 to 4, so that the MOS transistors 1 to 4 are all turned off to stop the operation of the charge pump circuit.
However, even though the operation of the charge pump circuit is stopped, the charge charged to the flying capacitor 5 is not discharged but maintained, and the voltage thereacross is VDD. When the charge pump circuit is activated again under this condition, a large current flows through the output capacitor 6 and the output voltage level abruptly changes as shown in FIG. 10. This is because the flying capacitor 5 is charged from the beginning, and even though the duty ratio of the rectangular wave outputted by the oscillation circuit 7 is low, a large current flows through the output capacitor 6 irrespective thereof. This phenomenon occurs every time the charge pump circuit is activated except when the charge pump circuit is activated for the first time.